1. Field of the Invention
The present invention relates in general to semiconductor devices and more particularly to semiconductor devices having reduced capacitance for protecting high frequency circuit applications from electrostatic discharge surge energy and transient electrical overstress.
2. Description of Related Art
In order to protect vulnerable circuits from electrical overstress such as that caused by electrostatic discharge, inductive load switching and lightning, a semiconductor device is usually employed to clamp the transient voltage to a nondestructive level. The semiconductor device for such transient voltage suppression purpose can be a diode, a transistor, a thyristor, an assembled device or a circuit.
Conventionally, a unidirectional protection device for such application is a Zener or avalanche diode constructed out of a semiconductor p-n junction (FIG. 1A). Based on semiconductor physics, the depletion-layer capacitance that arises inevitably across the one-sided abrupt junction for a p-n junction diode isCd=εSiA/WD=(qεSiND(VR+Vbi)/2)1/2A  (1)where εSi is the permittivity of silicon, q is the electric charge, ND is the doping concentration of the lightly doped region of the junction, VR is the reverse bias voltage across the diode, Vbi is the built-in potential, WD is the depletion-layer width of the junction and A is the junction area.
This capacitance is proportional to the square root of the doping concentration on the lightly doped side of the p-n junction. It is also proportional to the size of the overall junction area of the device. In a diode with breakdown voltage range of 5 to 20 volts, doping concentration on the lightly doped side ranges approximately from 1E17 to 5E18 atoms/cm3. The corresponding capacitance of the junction, assuming active p-n junction area of 0.1 mm2, is approximately 100 to 700 pF, which is relatively too high a value for high frequency applications.
To use such diodes in high frequency circuits it is generally necessary to reduce their capacitance to low pico- or even sub pico-Farad range. One simple approach is to combine the conventional unidirectional diode device with low capacitance switching diodes or p-i-n diodes in various circuit configurations. FIGS. 1B and 1C show an assembly of diodes having the same function as the conventional unidirectional diode device of FIG. 1A. This assembled device comprises of a conventional diode D3 and two p-i-n diodes, diode D2 used as a capacitance cancellation diode and diode D1 used as a current bypassing diode.
When the cathode of the assembled device is applied with a positive voltage relative to the anode, diode D3 is reverse biased, diode D2 is forward biased and diode D1 is reverse biased. The cathode current flows through the assembled device only when the cathode bias voltage is higher than the breakdown voltage of diode D3 plus the forward voltage drop of diode D2. When the cathode of the assembled device is applied with a negative voltage relative to the anode, diode D2 is reverse biased and blocks current flow through the forward biased diode D3. The cathode current flows completely through diode D1 which is under forward bias condition. Thus, diode D1 provides the current bypassing operation under forward bias, and let the entire assembled device act completely the same function as the conventional unidirectional diode device of FIG. 1A.
In the assembled device, the diode D3 is in series with the capacitance cancellation diode D2, resulting in a combined capacitance of CD3*CD2/(CD3+CD2)≅CD2, because CD3 is typically much larger than CD2 and can be neglected from the above relationship, and thus has no effect to the total capacitance of the combined diodes D3 and D2 structure. The entire assembled device is constructed by parallel arrangement of diode D1 with diodes D3/D2 combined structure, then, has a capacitance of CDevice≅CD1+CD2, which is substantially less than the capacitance CD3 of the conventional unidirectional diode device in FIG. 1A.
A conventional bidirectional diode device comprises two conventional unidirectional diode devices, connected in series and in a back-to-back configuration as shown in FIG. 2A. To reduce the capacitance of such a bidirectional diode device, FIGS. 2B and 2C show an assembled device comprising two pairs of diodes in an anti-parallel configuration. Each pair of diodes includes a conventional unidirectional diode D3 and a low capacitance switching diode or p-i-n diode D2, connected in a back-to-back configuration. When electrode 1 is positively biased relative to electrode 2, current flows through diodes D3_2 and D2_2. When electrode 2 is positively biased relative to electrode 1, current flows through diodes D3_1 and D2_1. The assembled device has a capacitance of CDevice≈2CD2, which is substantially less than the capacitance of the conventional bidirectional diode device in FIG. 2A.
In FIG. 2D, another assembled device, which functions similarly to a conventional bidirectional diode device of FIG. 2A, comprises a diode bridge including a conventional unidirectional diode device and four switching diodes or p-i-n diodes. When electrode 1 is positively biased relative to electrode 2, current flows through diodes D2_1, D3, and D1_1. When electrode 2 is positively biased relative to electrode 1, current flows through diodes D2_2, D3 and D1_2. The diode D3 is under reverse-biased breakdown in either case. The assembled device has a capacitance of CDevice≅CD2, which is substantially less than the capacitance of the conventional bidirectional diode device in FIG. 2A.
For example, a semiconductor device disclosed in U.S. Pat. No. 5,311,042, describes two monolithic integrated semiconductor structures. One structure includes an assembly of diodes in a configuration the same as in FIG. 1B, having function of a unidirectional assembled device, and another structure includes an assembly of diodes in a configuration the same as in FIG. 2D, having function of a bidirectional assembled device. According to this prior art, the diffusion technology is employed to fabricate the lightly doped side of D2 and the epitaxial technology to D1. By using a doping concentration of approximately 1E15 atoms/cm3 in the epitaxial layer and 1E16 atoms/cm3 at the interface of p-n junction in the diffusion region, the structure can be made with low capacitance.
For another example, a semiconductor device disclosed in U.S. Pat. No. 6,867,436, describes a bidirectional assembled device has a configuration the same as in FIG. 2B. Two pairs of diodes in an anti-parallel arrangement are made in different islands in the epitaxial layer grown on a silicon substrate, and separated by p+ isolation diffusion region in order to avoid interference between the two pair of diodes. In this prior art, diodes D2 have the lightly doped side of the diode made in the epitaxial layer. When the resistivity of the epitaxial layer of 70 ohm-cm, or doping concentration of approximately 6E13/cm3, is adopted, the entire device with low capacitance of less than 10 pF can be made.
Drawback 1:
In the prior art described in U.S. Pat. No. 5,311,042, the lightly doped side of the diode D2 is an n-type diffusion region. Doping concentration of a diffusion region is usually in the range of 5E15-1E18/cm3. The doping concentration in the lightly doped side of the diode D1, which usually is formed by epitaxial growth, can be in the range of 2E13-1E15/cm3. Then the value of CD2 is about 3 to 100 times that of CD1. The capacitance of the entire unidirectional assembled device is CDevice≅CD1+CD2, thus, CD2 dominates the total capacitance CDevice of the device.
Drawback 2:
In the prior art described in U.S. Pat. No. 6,867,436, it is inherently difficult to construct the device that achieves a device capacitance sufficiently low for any practical utilization in higher frequency circuit. This is because its structure needs a high-resistivity n− epitaxial layer with sufficient thickness to allow for full depletion inevitable for its physical operation in low capacitance range. Yet the long duration high temperature fabrication procedure in the p+ isolation diffusion incurs the spread out of the diffusion junction area that substantially reduces the thickness of its n− epitaxial layer. In fact, the effective thickness of the n− layer may be even reduced significantly due to the backward out-diffusion from the n+ buried layer and the n+ substrate in case it is used. This translates unfavorably into increased device capacitance. In order to compensate this effect, thicker epitaxial layer is adopted, and this will iteratively require longer diffusion for isolation region.
Drawback 3:
Typical isolation diffusion and deep n+ diffusion implemented for the fabrication of a conventional diode structure significantly consume the chip active area due to their long duration and high temperature procedure which results in the inevitable lateral diffusion.